? semiconductor components industries, llc, 2002 may, 2002 rev. 6 1 publication order number: mc10ep131/d mc10ep131, mc100ep131 3.3v / 5vecl quad d flip-flop with set, reset, and differential clock the mc10/100ep131 is a quad masterslaved d flipflop with common set and separate resets. the device is an expansion of the e131 with differential common clock and individual clock enables. with ac performance faster than the e131 device, the ep131 is ideal for applications requiring the fastest ac performance available. each flipflop may be clocked separately by holding common clock (c c ) low and c c high, then using the differential clock enable inputs for clocking (c 03 , c 03 ). common clocking is achieved by holding the differential inputs c 03 low and c 03 high while using the differential common clock (c c ) to clock all four flipflops. when left floating open, any differential input will disable operation due to input pulldown resistors forcing an output default state. individual asynchronous resets (r 03 ) and an asynchronous set (set) are provided. data enters the master when both c c and c 03 are low, and transfers to the slave when either c c or c 03 (or both) go high. the 100 series contains temperature compensation. ? 460 ps typical propagation delay ? maximum frequency > 3 ghz typical ? differential individual and common clocks ? individual asynchronous resets ? asynchronous set ? pecl mode operating range: v cc = 3.0 v to 5.5 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 3.0 v to 5.5 v ? open input default state ? safety clamp on inputs ? q output will default low with inputs open or at v ee 32 1 mcxxx awlyyww ep131 lqfp32 fa suffix case 873a marking diagram* xxx = 10 or 100 a = assembly location wl = wafer lot yy = year ww = work week *for additional information, see application note and8002/d device package shipping ordering information mc10ep131fa lqfp32 250 units/tray mc10ep131far2 lqfp32 2000 tape & reel mc100ep131fa lqfp32 250 units/tray mc100ep131far2 lqfp32 2000 tape & reel http://onsemi.com
mc10ep131, mc100ep131 http://onsemi.com 2 v ee 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 r 1 c 0 c 0 v cc d 0 r 0 v cc d 2 set r 3 d 3 v ee c 3 c 3 v cc d 1 c 1 c 1 c c c c c 2 r 2 q 0 q 0 q 1 q 1 q 2 q 2 q 3 q 3 32lead lqfp pinout (top view) c 2 pin description pin d 03 * ecl data inputs function c 03 *, c 03 * c c *, c c * ecl common clock inputs ecl separate clock inputs r 03 * ecl asynchronous reset set* ecl asynchronous set q 03 , q 03 ecl data outputs v cc positive supply v ee negative supply d 3 c 3 r 3 d 2 c 2 r 2 set c c r 1 c 1 d 1 r 0 c 0 d 0 q 3 q 3 q 2 q 2 q 1 q 1 q 0 q 0 s d q q r s d q q r r d q q s r d q q s c 3 c 2 c 1 c 0 c c figure 1. 32lead lqfp pinout (top view) warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. figure 2. logic diagram * pins will default low when left open. v ee attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor n/a esd protection human body model machine model charged device model > 2 kv > 100 v > 2 kv moisture sensitivity (note 1) level 2 flammability rating oxygen index: 28 to 34 ul 94 v0 @ 0.125 in transistor count 935 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d.
mc10ep131, mc100ep131 http://onsemi.com 3 maximum ratings (note 2) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v 6 v v i pecl mode input voltage v ee = 0 v v i v cc 6 v v i pecl mode in ut voltage necl mode input voltage v ee 0 v v cc = 0 v v i ? ?? ? ? v ee 6 6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma t a operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junctiontoambient) 0 lfpm 500 lfpm 32 lqfp 32 lqfp 80 55 c/w c/w q jc thermal resistance (junctiontocase) std bd 32 lqfp 12 to 17 c/w t sol wave solder > 2 to 3 sec @ 248 c 265 c 2. maximum ratings are those values beyond which device damage may occur. 10ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 3) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 70 95 120 70 95 120 70 95 120 ma v oh output high voltage (note 4) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mv v ol output low voltage (note 4) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mv v ih input high voltage (singleended) 2090 2415 2155 2480 2215 2540 mv v il input low voltage (singleended) 1365 1690 1460 1755 1490 1815 mv v ihcmr input high voltage common mode range (differential) (note 5) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.5 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to 2.2 v. 4. all loading with 50 w to v cc 2.0 volts. 5. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 10ep dc characteristics, pecl v cc = 5.0 v, v ee = 0 v (note 6) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 70 95 120 70 95 120 70 95 120 ma v oh output high voltage (note 7) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mv v ol output low voltage (note 7) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mv v ih input high voltage (singleended) 3790 4115 3855 4180 3915 4240 mv v il input low voltage (singleended) 3065 3390 3130 3455 3190 3515 mv v ihcmr input high voltage common mode range (differential) (note 8) 2.0 5.0 2.0 5.0 2.0 5.0 v i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.5 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. input and output parameters vary 1:1 with v cc . v ee can vary +2.0 v to 0.5 v. 7. all loading with 50 w to v cc 2.0 volts. 8. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep131, mc100ep131 http://onsemi.com 4 10ep dc characteristics, necl v cc = 0 v, v ee = 5.5 v to 3.0 v (note 9) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 70 95 120 70 95 120 70 95 120 ma v oh output high voltage (note 10) 1135 1010 885 1070 945 820 1010 885 760 mv v ol output low voltage (note 10) 1935 1810 1685 1870 1745 1620 1810 1685 1560 mv v ih input high voltage (singleended) 1210 885 1145 820 1085 760 mv v il input low voltage (singleended) 1935 1610 1870 1545 1810 1485 mv v ihcmr input high voltage common mode range (differential) (note 11) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.5 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. input and output parameters vary 1:1 with v cc . 10. all loading with 50 w to v cc 2.0 volts. 11. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 100ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 12) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 70 95 120 75 97 120 80 105 130 ma v oh output high voltage (note 13) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 13) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv v ih input high voltage (singleended) 2075 2420 2075 2420 2075 2420 mv v il input low voltage (singleended) 1355 1675 1355 1675 1355 1675 mv v ihcmr input high voltage common mode range (differential) (note 14) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.5 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 12. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to 2.2 v. 13. all loading with 50 w to v cc 2.0 volts. 14. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 100ep dc characteristics, pecl v cc = 5.0 v, v ee = 0 v (note 15) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 70 95 120 75 97 120 80 105 130 ma v oh output high voltage (note 16) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mv v ol output low voltage (note 16) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mv v ih input high voltage (singleended) 3775 4120 3775 4120 3775 4120 mv v il input low voltage (singleended) 3055 3375 3055 3375 3055 3375 mv v ihcmr input high voltage common mode range (differential) (note 17) 2.0 5.0 2.0 5.0 2.0 5.0 v i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.5 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 15. input and output parameters vary 1:1 with v cc . v ee can vary +2.0 v to 0.5 v. 16. all loading with 50 w to v cc 2.0 volts. 17. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep131, mc100ep131 http://onsemi.com 5 100ep dc characteristics, necl v cc = 0 v, v ee = 5.5 v to 3.0 v (note 18) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 70 95 120 75 97 120 80 105 130 ma v oh output high voltage (note 19) 1145 1020 895 1145 1020 895 1145 1020 895 mv v ol output low voltage (note 19) 1945 1820 1695 1945 1820 1695 1945 1820 1695 mv v ih input high voltage (singleended) 1225 880 1225 880 1225 880 mv v il input low voltage (singleended) 1945 1625 1945 1625 1945 1625 mv v ihcmr input high voltage common mode range (differential) (note 20) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.5 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 18. input and output parameters vary 1:1 with v cc . 19. all loading with 50 w to v cc 2.0 volts. 20. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. ac characteristics v cc = 0 v; v ee = 3.0 v to 5.5 v or v cc = 3.0 v to 5.5 v; v ee = 0 v (note 21) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum frequency (see figure 3. frequency vs. v outpp and jitter) > 3 > 3 > 3 ghz t plh , t phl propagation delay to c 03 output differential c c r 03 set 320 320 320 300 450 450 430 430 520 520 520 550 380 400 380 380 460 500 480 460 580 600 580 580 450 450 450 400 560 560 560 530 650 650 700 650 ps t rr set/r03 recovery 290 210 290 210 350 280 ps t s t h setup time hold time 120 80 120 80 120 80 ps t pw minimum pulse rate set, r 03 550 400 550 400 550 400 t jitter cycletocycle jitter (see figure 3. frequency vs. v outpp and jitter) 0.2 < 1 0.2 < 1 0.2 < 1 ps t r t f output rise/fall times q, q (20% 80%) 110 180 250 125 200 275 150 230 300 ps 21. measured using a 750 mv source, 50% duty cycle clock source. all loading with 50 w to v cc 2.0 v.
mc10ep131, mc100ep131 http://onsemi.com 6 0 100 200 300 400 500 600 700 800 0 1000 2000 3000 4000 5000 6000 figure 3. frequency vs. v outpp and jitter frequency (mhz) 1 2 3 4 5 6 7 8 (jitter) v outpp (mv) jitter out ps (rms) driver device receiver device d d q q 50 w 50 w v tt figure 4. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) v tt = v cc 2.0 v resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8009 eclinps plus spice i/o model kit and8020 termination of ecl logic devices for an updated list of application notes, please see our website at http://onsemi.com.
mc10ep131, mc100ep131 http://onsemi.com 7 package dimensions detail y a s1 v b 1 8 9 17 25 32 ae ae p detail y base n j d f metal section aeae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc detail ad a1 b1 v1 4x s 4x b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref 9 t z u t-u 0.20 (0.008) z ac t-u 0.20 (0.008) z ab 0.10 (0.004) ac ac ab m 8x t, u, z t-u m 0.20 (0.008) z ac notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -ab- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -t-, -u-, and -z- to be determined at datum plane -ab-. 5. dimensions s and v to be determined at seating plane -ac-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -ab-. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. lqfp fa suffix 32lead plastic package case 873a02 issue a
mc10ep131, mc100ep131 http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc10ep131/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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